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| devices incorporated video imaging products 2-1 LF2301 image resampling sequencer 08/16/2000Clds.2301-h q q q q q 40 mhz clock rate q q q q q high-speed image manipulation q q q q q maximum image size: 4096 x 4096 pixels q q q q q supports following interpolation algorithms: ? nearest-neighbor ? bilinear interpolation ? cubic convolution q q q q q applications: ? video special-effects ? image recognition ? high-speed data encoding/ decoding q q q q q replaces trw/raytheon/fairchild tmc2301 q q q q q 68-pin plcc, j-lead features description LF2301 image resampling sequencer devices incorporated LF2301 b lock d iagram source address generator target address generator input image boundary comparator acc done wen ldr b 3-0 p 11-0 inter init noop end parameter storage control integer fraction czero u 11-0 uwri x 11-0 ca 7-0 walk count oeta the LF2301 is a self-sequencing address generator designed to filter a two-dimensional image or remap and resample it from one set of cartesian coordinates (x,y) into a new set (u,v). the LF2301 can resample digitized images or perform such manipula- tions as rotation, panning, zooming, and warping as well as compression in real-time. by using two LF2301s in a image transformation system (its), nearest-neighbor, bilinear interpola- tion, and cubic convolution algo- rithms, with kernel sizes up to 4 x 4 pixels, are all possible (see figure 1). this system can also implement simple static filters with kernel sizes up to 16 x 16 pixels. details of operation most video applications use a pair of LF2301s in tandem to construct an its. one LF2301 is the row coordinate generator (x to u) and the other is the column generator (y to v). external ram is needed for storage of the interpolation coeffi- cient lookup table, as well as for buffers of the source and destination images. an external multiplier- accumulator is required when performing interpolation or imple- menting static filters. the its is capable of performing the general second-order coordinate transformation of the form: x(u,v) = au 2 +bu+cuv+dv 2 +ev+f y(u,v) = gu 2 +hu+kuv+lv 2 +mv+n where parameters a through n of the transform are user-defined. the system steps sequentially through each pixel in the target image lying within a user-defined rectangle. for each target pixel at (u,v), the LF2301 points to a corresponding source pixel at (x,y).
devices incorporated LF2301 image resampling sequencer 2-2 08/16/2000Clds.2301-h video imaging products signal definitions power vcc and gnd +5v power supply. all pins must be connected. clock clk master clock the rising edge of clk strobes all enabled registers. inputs p 11-0 parameter register data input p 11-0 is the 12-bit parameter register data input port. p 11-0 is latched on the rising edge of clk. b 3-0 parameter register address input b 3-0 is the 4-bit parameter register address input port. b 3-0 is latched on the rising edge of clk. outputs x 11-0 source address output x 11-0 is the 12-bit registered source address output port. ca 7-0 coefficient address output ca 7-0 is the 8-bit registered coeffi- cient address output port. u 11-0 target address output u 11-0 is the 12-bit registered target address output port. controls init initialize when init is high for a minimum of two clock cycles, the control logic is cleared and initialized for the start of a new image transformation. when init goes low, normal operation begins after two clock cycles. init is latched on the rising edge of clk. wen write enable when wen is low, data latched into the device on p 11-0 is loaded into the preload register addressed by the data latched into the device on b 3-0 . when wen is high, data cannot be loaded into the preload registers and their contents will not be changed. wen is latched on the rising edge of clk. ldr load data register when ldr is high, data in all preload registers is latched into the transformation parameter registers. when ldr is low, data cannot be loaded into the transformation parameter registers and their contents will not be changed. ldr is latched on the rising edge of clk. acc accumulate the registered acc output initializes the accumulation register of the external multiplier-accumulator. at the start of each interpolation walk, acc goes low for one cycle effec- tively clearing the storage register by loading in only the new first product. acc from either the row or column LF2301 may be used. uwri target memory write enable the target memory write enable goes low for one clock cycle after the end of each interpolation walk. when oeta is high, this registered output is forced to the high-impedance state. uwri from either the row or column LF2301 may be used. inter interconnect when two LF2301s are used to form an its, the end flag on each device is connected to inter on the other device. the end flag from the row device indicates an end of line to the column device. the end flag from the column device indicates a bottom of frame to the row device, forcing a reset of the address counter. noop no operation when noop is low, the clock is overridden holding all address generators in their current state. x 11-0 and ca 7-0 are forced to the high- f igure 1. i mage t ransformation s ystem (its) 12 p 11-0 5 init, ldr, b 3-0 4 inter end inter end 12 24 12 12 12 12 24 LF2301 row address generator (x) x 11-0 acc uwri u 11-0 8 8 image data in 12 12 image data out v 11-0 y 11-0 LF2301 column address generator (y) interpolation coefficient ram ca 7-0 clk acc destination image ram lma1009/2009 12 x 12 bit multiplier- accumulator source image ram ca 7-0 y x x,y,p d out 12 12 wen, noop, oeta devices incorporated video imaging products 2-3 LF2301 image resampling sequencer 08/16/2000Clds.2301-h impedance state. users may then access external memory. normal operation resumes on the next clock cycle after noop goes high. noop is latched on the rising edge of clk. oeta target memory output enable when oeta is high, uwri and u 11-0 are forced to the high-impedance state. when oeta is low, uwri and u 11-0 are enabled on the next clock cycle. oeta is latched on the rising edge of clk. flags czero coefficient zero if in a row device x<0, xmin x xmax, or x 3 4096, the registered czero flag goes high . if 0 x < xmin or xmax devices incorporated LF2301 image resampling sequencer 2-4 08/16/2000Clds.2301-h video imaging products t able 3. f ield o f v iew f 2 f 1 f 0 fov 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 r/c row/column select when set to 0, the LF2301 functions as a row device. when set to 1, the LF2301 functions as a column device. m 1-0 mode this 2-bit control word defines four modes as follows (see table 1): the 1st and 3rd modes are single- pass operations where the device walks through a (k + 1) x (k + 1) kernel for each output pixel. k is the kernel size determined by k 3-0 in parameter register 7. in mode 00, the spiral walk is in the clockwise direc- tion. in mode 10, the spiral walk is in the counter clockwise direction. the 2nd and 4th modes are used together to perform a two-pass operation. the first pass (mode 01) performs a (k+1) kernel in the horizontal dimension. the second pass (mode 11) performs a (k+1) kernel in the vertical dimension. the result of pass 1 is stored in the destination image memory and is used as the source image data for the second pass. a system to switch source and destination memory banks could be designed, or utilization of a second LF2301 pair in a pipelined architecture could be used. in this case, the system would require a third image buffer for the final destination image. k 3-0 kernel kernel determines the length of the spiral walk when performing image transformations and the size of the filter when implementing static filters (see table 2). when performing image transformations, the longest spiral walk possible is 4 x 4 pixels (kernel = 3). for static filters, kernels of up to 16 x 16 pixels (kernel = 15) are possible. fov field of view fov determines the distance between pixels in a spiral walk. an fov of 1 means each step in a spiral walk is one pixel. an fov of 2 means each step is two pixels, and so on. fov can be set as high as 7 (see table 3). it is impor- tant to note when fov is 0, the x and y addresses will not change during a spiral walk. they will remain fixed at the first pixel address of the spiral walk. alr autoload when set high and upon init being strobed, the ldr control is automatically asserted which causes the data currently stored in the preload registers to be loaded into the transformation parameter registers. ain autoinit a new transform automatically begins if the ain bit is high when the end of an image is reached. the done flag will go high for one clock cycle. if ain is low, uwri and the done flag remain high until the user strobes the init control to begin a new image transformation. pipe pipe control in order to compensate for buffered source image ram, pipe adjusts the timing of uwri and acc. if the pipe bit is high, uwri and acc will have a one clock cycle delay added relative to the generation of the target address. tm test mode calculations of the source image and coefficient addresses are made by an internal 28-bit accumulator. tm allows access to the sign bit and the seven bits below the four coefficient address bits in the accumulator. when tm is high the sign bit and 11 bits below the source image address are fed to x 11-0 (see figure 2). when tm is low, the source image address is fed to x 11-0 . two clock cycles are required to access both the ms and ls words of the internal accumulator. functional description the LF2301 is an address generator designed to be used in an image transformation system (its). when implementing an LF2301-based its, second-order image transformations can be performed like resampling, rotation, warping, panning, and rescaling, all at real-time video rates. 2d filtering operations, like pixel convolutions, can also be performed. in most applications two LF2301s are used, one to generate the row addresses and the other to generate the column t able 1. m ode s election m 1 m 0 mode 0 0 single-pass operation (cw) 0 1 pass 1 of two-pass operation 1 0 single-pass operation (ccw) 1 1 pass 2 of two-pass operation t able 2. k ernel k 3 k 2 k 1 k 0 kernel 00 00 1 x 1 00 01 2 x 2 00 10 3 x 3 00 11 4 x 4 01 00 5 x 5 01 01 6 x 6 01 10 7 x 7 01 11 8 x 8 10 00 9 x 9 10 0110 x 10 10 1011 x 11 10 1112 x 12 11 0013 x 13 11 0114 x 14 11 1015 x 15 11 1116 x 16 devices incorporated video imaging products 2-5 LF2301 image resampling sequencer 08/16/2000Clds.2301-h addresses. an example of an its implemented with two LF2301s is shown in figure 1. in this system the following components are used: two LF2301s, a multiplier-accumulator (mac), interpolation coefficient ram, and source/target image ram. maximum image size is 4096 x 4096 pixels. data word size is determined by the word size of the external ram. a typical its performs image transfor- mations as follows: a. the LF2301s generate sequential pixel addresses (left to right, top to bottom) which fill the rectangle in the target image ram defined by (umin,vmin) and (umax +1, vmax). it is important to note that the u value of the last pixel address on each line of the target ram is umax + 1. b. the LF2301s calculate the address of the corresponding pixel in the source image ram for each target pixel address generated. c. if interpolation is needed, the external mac sums the products of the source pixels and the interpola- tion coefficients. control signals for the mac and address signals for the interpolation coefficient ram are provided by the LF2301s. d. the new pixel value is written into the target image ram. the LF2301s generate source pixel addresses according to the following general second order equations: x = au 2 + bu + cuv + dv 2 + ev + f y = gu 2 + hu + kuv + lv 2 + mv + n where (x,y) and (u,v) are the source and target coordinates respectively. a through n are user-defined param- eters. the actual second order equa- tions used are shown in figure 3. dx du d x dudv 2 dx dv d x 2 du 2 d x 2 dv 2 m C m 2 2 n C n 2 2 + = x 0 m+ n+ mn+ + x dy du d y dudv 2 dy dv d y 2 du 2 d y 2 dv 2 m C m 2 2 n C n 2 2 + = y 0 m+ n+ mn+ + y + fov cay(w) fov m cay(ker) + + fov cax(w) fov m cax(ker) + m = u umin + n = v vmin + note: m C m 2 2 approximates the exponential characteristic of m 2 . f igure 3. a ddress t ransformation e quations f igure 2. t est m ode d ata r outing sign 7 4 12 1 ca 3-0 ca 7-4 x 11-0 /t 11-0 28-bit internal accumulator walk counter 4 4 12 12 devices incorporated LF2301 image resampling sequencer 2-6 08/16/2000Clds.2301-h video imaging products addr msb format lsb row column 0000 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 xmin ymin 0001 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 xmax ymax 0010 2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 C1 2 C2 2 C3 2 C4 2 C5 x 0 (ls) y 0 (ls) 0011 alr ain pipe r/c m 1 m 0 C2 12 2 11 2 10 2 9 2 8 2 7 controls, x 0 (ms) controls, y 0 (ls) 0100 2 C1 2 C2 2 C3 2 C4 2 C5 2 C6 2 C7 2 C8 2 C9 2 C10 2 C11 2 C12 dx/du (ls) dy/du (ls) 0101 tm f 2 f 1 f 0 C2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 controls, dx/du (ms) controls, dy/du (ms) 0110 2 C1 2 C2 2 C3 2 C4 2 C5 2 C6 2 C7 2 C8 2 C9 2 C10 2 C11 2 C12 dx/dv (ls) dy/dv (ls) 0111 k 3 k 2 k 1 k 0 C2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 kernel, dx/dv (ms) kernel, dy/dv (ms) 1000 2 C9 2 C10 2 C11 2 C12 2 C13 2 C14 2 C15 2 C16 2 C17 2 C18 2 C19 2 C20 d 2 x/dudv (ls) d 2 y/dudv (ls) 1001 C2 3 2 2 2 1 2 0 2 C1 2 C2 2 C3 2 C4 2 C5 2 C6 2 C7 2 C8 d 2 x/dudv (ms) d 2 y/dudv (ms) 1010 2 C9 2 C10 2 C11 2 C12 2 C13 2 C14 2 C15 2 C16 2 C17 2 C18 2 C19 2 C20 d 2 x/du 2 (ls) d 2 y/du 2 (ls) 1011 C2 3 2 2 2 1 2 0 2 C1 2 C2 2 C3 2 C4 2 C5 2 C6 2 C7 2 C8 d 2 x/du 2 (ms) d 2 y/du 2 (ms) 1100 2 C9 2 C10 2 C11 2 C12 2 C13 2 C14 2 C15 2 C16 2 C17 2 C18 2 C19 2 C20 d 2 x/dv 2 (ls) d 2 y/dv 2 (ls) 1101 C2 3 2 2 2 1 2 0 2 C1 2 C2 2 C3 2 C4 2 C5 2 C6 2 C7 2 C8 d 2 x/dv 2 (ms) d 2 y/dv 2 (ms) 1110 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 umin vmin 1111 2 11 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 umax vmax t able 4. p arameter r egister f ormats (r ow or c olumn m ode ) transformation parameter register loading the LF2301 allows transformation parameters to be updated on-the-fly. the loading of these registers is double-buffered (see figure 4). any or all of the first level registers can be loaded using p 11-0 , b 3-0 , and wen without affecting the param- eters currently in use. ldr simultaneously updates all transformation parameter registers. if autoload (alr) is active, these registers will be updated automati- cally at the beginning of each new image. note that noop does not affect the loading of the transforma- tion parameter registers. f igure 4. ldr c ontrol for p arameter u pdate decode 4 12 wen clk b 3-0 c15 c14 c13 c2 c1 ldr c0 preload registers transformation parameter registers p 11-0 devices incorporated video imaging products 2-7 LF2301 image resampling sequencer 08/16/2000Clds.2301-h static filter static filtering at real-time video rates can be performed as shown in figure 5. this mode is selected by loading m 1-0 with 00 for a clock- wise spiral walk. a counterclock- wise spiral walk could be selected by loading m 1-0 with 10. in this example, a static filter with a kernel size of 3 x 3 pixels is desired. load- ing k 3-0 with 0010 selects a kernel size of 3 x 3. the first pixel selected is determined by x 0 and y 0 . in this example, the first pixel is (6,6). in this case, the LF2301s should ad- dress consecutive pixels during each spiral walk. for this to occur, fov must be set to 1 (f 2-0 loaded with 001). after the last pixel of a spiral walk has been selected, the next pixel address is determined by adding dx/du to the current x address and by adding dy/du to the current y address (unless the kernel just completed was the last for that line). at the end of the first spiral walk, pixel (7,5) is addressed. since the first pixel of the next spiral walk should be (7,6), dx/du is selected to be 0 and dy/du is selected to be 1. after the last pixel of the last spiral walk on the first line has been selected, the first pixel address of the second line is determined by adding dx/dv to x 0 and by adding dy/dv to y 0 . since the first pixel of the first spiral walk on the second line should be (6,7), dx/dv is selected to be 0 and dy/dv is se- lected to be 1. second order differ- ential terms are not used in this filter and are therefore set to 0. umin and vmin are both selected to be 6. umax and vmax are both selected to be 7. table 5 shows the values loaded into all parameter registers. table 6 shows the its outputs for the 3 x 3 static filter. t able 5. p arameter r egisters addr row (hex) column (hex) 0000 000 000 0001 fff fff 0010 0c0 0c0 0011 000 100 0100 000 000 0101 100 101 0110 000 000 0111 200 201 1000 000 000 1001 000 000 1010 000 000 1011 000 000 1100 000 000 1101 000 000 1110 006 006 1111 007 007 1 = 1st pixel of 1st spiral walk, 2 = 1st pixel of 2nd spiral walk, etc. 4 6789 5 6 7 8 12 5 f igure 5. 3 3 s tatic f ilter devices incorporated LF2301 image resampling sequencer 2-8 08/16/2000Clds.2301-h video imaging products t able 6. its o utputs f or 3 3 s tatic f ilter cycle x y ca x (hex) ca y (hex) u v init acc uwri end x end y done 1 66 00 00 xx101000 2 66 00 00 xx001000 3 66 00 00 xx001000 4 66 00 00 xx001000 5 76 01 01 xx010000 6 77 02 02 xx011000 7 67 03 03 xx011000 8 57 04 04 xx011000 9 56 05 05 xx011000 10 55 06 06 xx011000 11 65 07 07 xx011100 12 75 08 08 xx011100 13 76 00 00 66001100 14 86 01 01 66010100 15 87 02 02 66011100 16 77 03 03 66011100 17 67 04 04 66011100 18 66 05 05 66011100 19 65 06 06 66011100 20 75 07 07 66011000 21 85 08 08 66011000 22 86 00 00 76001000 23 96 01 01 76010000 24 97 02 02 76011000 25 87 03 03 76011000 26 77 04 04 76011000 27 76 05 05 76011000 28 75 06 06 76011000 29 85 07 07 76011010 30 95 08 08 76011010 31 67 00 00 86001010 32 77 01 01 86010010 33 78 02 02 86011010 34 68 03 03 86011010 35 58 04 04 86011010 36 57 05 05 86011010 37 56 06 06 86011010 38 66 07 07 86011110 39 76 08 08 86011110 40 77 00 00 67001110 41 87 01 01 67010110 42 88 02 02 67011110 43 78 03 03 67011110 44 68 04 04 67011110 45 67 05 05 67011110 46 66 06 06 67011110 47 76 07 07 67011010 48 86 08 08 67011010 49 87 00 00 77001010 50 97 01 01 77010010 51 98 02 02 77011010 52 88 03 03 77011010 53 78 04 04 77011010 54 77 05 05 77011010 55 76 06 06 77011010 56 86 07 07 77011001 57 96 08 08 77011001 58 66 00 00 87001001 devices incorporated video imaging products 2-9 LF2301 image resampling sequencer 08/16/2000Clds.2301-h image rotation & bilinear interpolation figure 8 shows an example of rotating an image 30o and using bilinear interpolation. this mode is selected by loading m 1-0 with 00 for a clockwise spiral walk. a counterclockwise spiral walk could be selected by loading m 1-0 with 10. bilinear interpolation requires a kernel size of 2 x 2 pixels. loading k 3-0 with 0001 selects a kernel size of 2 x 2. the first pixel selected is determined by x 0 and y 0 . in this example, the first pixel is (0,0). in this case, the LF2301s should address consecutive pixels during each spiral walk. for this to occur, fov must be set to 1 (f 2-0 loaded with 001). after the last pixel of a spiral walk has been selected, the next pixel address is determined by adding dx/du to the current x address and by adding dy/du to the current y address (unless the kernel just completed was the last for that line). at the end of the first spiral walk, pixel (0,1) is ad- dressed. since the next calculated pixel should be (0.866,0.5), dx/du is selected to be 0.866 and dy/du is selected to be 0.5. however, after adding dx/du and dy/du to the x and y addresses respectively, the generated address is (0.866,1.5). the y address is off by a value of 1. this is due to the fact that the last pixel address of a spiral walk is used to calculate the first pixel address of the next spiral walk. in order for the LF2301s to generate the correct result, dy/du must be modified by subtract- ing a 1 from it. the correct value of dy/du is -0.5. figure 6 shows how the unmodified differential terms were calculated. after the last pixel of the last spiral walk on the first line has been selected, the first pixel address of the second line is determined by adding dx/dv to x 0 and by adding dy/dv to y 0 . since the first calculated pixel of the first t able 7. p arameter r egisters addr row (hex) column (hex) 0000 000 000 0001 fff fff 0010 000 000 0011 000 100 0100 ddb 800 0101 100 1ff 0110 800 ddb 0111 1ff 100 1000 000 000 1001 000 000 1010 000 000 1011 000 000 1100 000 000 1101 000 000 1110 000 000 1111 002 002 spiral walk on the second line should be (-0.5,0.866), dx/dv is selected to be -0.5 and dy/dv is selected to be 0.866. second order differential terms are not used in this transform and are therefore set to 0. it is important to note that the integer portion of the address generated in the LF2301 is used as the x or y pixel address. the fractional portion (sub-pixel portion) is used as the coefficient ram address. umin and vmin are both selected to be 0. umax and vmax are both selected to be 2. table 7 shows the values loaded into all parameter registers. table 8 shows the its outputs for this example. 30 o length =1 dx dv dx du dy du dy dv y x v u calculated pixels source image pixels f igure 7. 30 i mage r otation 1,2 34 5 0123 1 2 3 4 1 = 1st pixel of 1st spiral walk, calculated pixels 0 -1 source image pixels 2 = 1st pixel of 2nd spiral walk, etc. f igure 8. 30 i mage r otation f igure 6. d ifferential t erms dx du dx dv = cos 30 o dy du dy dv = = = = 0.866 sin 30 o = 0.5 Csin 30 o = C0.5 cos 30 o = 0.866 devices incorporated LF2301 image resampling sequencer 2-10 08/16/2000Clds.2301-h video imaging products t able 8. its o utputs f or 30 i mage r otation w ith b ilinear i nterpolation cycle x y ca x (hex) ca y (hex) u v init acc uwri end x end y done 1 00 00 00 xx101000 2 00 00 00 xx001000 3 00 00 00 xx001000 4 00 00 00 xx001000 5 10 01 01 xx010000 6 11 02 02 xx011000 7 01 03 03 xx011000 8 00 d0 80 00001000 9 10 d1 81 00010000 10 11 d2 82 00011100 11 01 d3 83 00011100 12 11 b0 00 10001100 13 21 b1 01 10010100 14 22 b2 02 10011000 15 12 b3 03 10011000 16 21 90 80 20001000 17 31 91 81 20010000 18 32 92 82 20011000 19 22 93 83 20011000 20 -10 80 d0 30001000 21 00 81 d1 30010000 22 01 82 d2 30011000 23 -11 83 d3 30011000 24 01 50 50 01001000 25 11 51 51 01010000 26 12 52 52 01011100 27 02 53 53 01011100 28 11 30 d0 11001100 29 21 31 d1 11010100 30 22 32 d2 11011000 31 12 33 d3 11011000 32 22 10 50 21001000 33 32 11 51 21010000 34 33 12 52 21011010 35 23 13 53 21011010 36 -11 00 b0 31001010 37 01 01 b1 31010010 38 02 02 b2 31011010 39 -12 03 b3 31011010 40 -12 d0 30 02001010 41 02 d1 31 02010010 42 03 d2 32 02011110 43 -13 d3 33 02011110 44 02 b0 b0 12001110 45 12 b1 b1 12010110 46 13 b2 b2 12011010 47 03 b3 b3 12011010 48 13 90 30 22001010 49 23 91 31 22010010 50 24 92 32 22011001 51 14 93 33 22011001 52 00 00 00 32001001 53 10 01 01 32010001 54 11 02 02 32011001 55 01 03 03 32011001 devices incorporated video imaging products 2-11 LF2301 image resampling sequencer 08/16/2000Clds.2301-h t able 10. its o utputs f or p ass 1 o f t wo -p ass cycle x y ca x (hex) ca y (hex) u v init acc uwri end x end y done 1 00 00 00 xx101000 2 00 00 00 xx001000 3 00 00 00 xx001000 4 00 00 00 xx001000 5 10 01 01 xx010100 6 20 02 02 xx011100 7 10 00 00 55001100 8 20 01 01 55010000 9 30 02 02 55011000 10 20 00 00 65001000 11 30 01 01 65010010 12 40 02 02 65011010 13 01 00 00 75001010 14 11 01 01 75010110 15 21 02 02 75011110 16 11 00 00 56001110 17 21 01 01 56010010 18 31 02 02 56011010 19 21 00 00 66001010 20 31 01 01 66010001 21 41 02 02 66011001 22 00 00 00 76001001 23 10 01 01 76010101 24 20 02 02 76011101 pass 1 of two-pass operation pass 1 of the two-pass operation performs horizontal filtering on an image as shown in figure 9. this mode is selected by loading m 1-0 with 01. in this example, a horizontal filter with a kernel size of 3 pixels is desired. loading k 3-0 with 0010 selects a kernel size of 3. the first pixel selected is determined by x 0 and y 0 . in this example, the first pixel is (0,0). in this case, the LF2301s should address consecutive pixels during each pixel walk. for this to occur, fov must be set to 1 (f 2-0 loaded with 001). after the last pixel of a pixel walk has been selected, the next pixel address is determined by adding dx/du to the current x address and by adding dy/ du to the current y address (unless the kernel just completed was the last for that line). at the end of the first pixel walk, pixel (2,0) is addressed. since the first pixel of the next pixel walk should be (1,0), dx/du is selected to be -1 and dy/du is selected to be 0. after the last pixel of the last pixel walk on the first line has been selected, the first pixel address of the second line is determined by adding dx/dv to x 0 and by adding dy/dv to y 0 . since the first pixel of the first pixel walk on the second line should be (0,1), dx/dv is selected to be 0 and dy/dv is selected to be 1. second order differential terms are not used in this filter and are therefore set to 0. t able 9. p arameter r egisters addr row (hex) column (hex) 0000 000 000 0001 fff fff 0010 000 000 0011 040 140 0100 000 000 0101 1ff 000 0110 000 000 0111 200 201 1000 000 000 1001 000 000 1010 000 000 1011 000 000 1100 000 000 1101 000 000 1110 005 005 1111 006 006 umin and vmin are both selected to be 5. umax and vmax are both selected to be 6. table 9 shows the values loaded into all parameter registers. table 10 shows the its outputs for the pass 1 of a two-pass operation. 1 = 1st pixel of 1st walk, 2 = 1st pixel of 2nd walk, etc. -1 1234 0 1 2 3 123 6 45 7 0 f igure 9. p ass 1 o f t wo -p ass devices incorporated LF2301 image resampling sequencer 2-12 08/16/2000Clds.2301-h video imaging products t able 12. its o utputs f or p ass 2 o f t wo -p ass cycle x y ca x (hex) ca y (hex) u v init acc uwri end x end y done 1 00 00 00 xx101000 2 00 00 00 xx001000 3 00 00 00 xx001000 4 00 00 00 xx001000 5 01 01 01 xx010100 6 02 02 02 xx011100 7 10 00 00 55001100 8 11 01 01 55010000 9 12 02 02 55011000 10 20 00 00 65001000 11 21 01 01 65010010 12 22 02 02 65011010 13 01 00 00 75001010 14 02 01 01 75010110 15 03 02 02 75011110 16 11 00 00 56001110 17 12 01 01 56010010 18 13 02 02 56011010 19 21 00 00 66001010 20 22 01 01 66010001 21 23 02 02 66011001 22 00 00 00 76001001 23 01 01 01 76010101 24 02 02 02 76011101 pass 2 of two-pass operation pass 2 of the two-pass operation performs vertical filtering on an image as shown in figure 10. this mode is selected by loading m 1-0 with 11. in this example, a vertical filter with a kernel size of 3 pixels is desired. loading k 3-0 with 0010 selects a kernel size of 3. the first pixel se- lected is determined by x 0 and y 0 . in this example, the first pixel is (0,0). in this case, the LF2301s should address consecutive pixels during each pixel walk. for this to occur, fov must be set to 1 (f 2-0 loaded with 001). after the last pixel of a pixel walk has been selected, the next pixel address is determined by adding dx/du to the current x address and by adding dy/du to the current y address (unless the kernel just completed was the last for that line). at the end of the first pixel walk, pixel (0,2) is addressed. since the first pixel of the next pixel walk should be (1,0), dx/du is selected to be 1 and dy/du is selected to be -2. after the last pixel of the last pixel walk on the first line has been selected, the first pixel address of the second line is determined by adding dx/dv to x 0 and by adding dy/dv to y 0 . since the first pixel of the first pixel walk on the second line should be (0,1), dx/dv is selected to be 0 and dy/dv is selected to be 1. second order differential terms are not used in this filter and are therefore set to 0. t able 11. p arameter r egisters addr row (hex) column (hex) 0000 000 000 0001 fff fff 0010 000 000 0011 0c0 1c0 0100 000 000 0101 101 1fe 0110 000 000 0111 200 201 1000 000 000 1001 000 000 1010 000 000 1011 000 000 1100 000 000 1101 000 000 1110 005 005 1111 006 006 umin and vmin are both selected to be 5. umax and vmax are both selected to be 6. table 11 shows the values loaded into all parameter registers. table 12 shows the its outputs for the pass 2 of a two-pass operation. 1 = 1st pixel of 1st walk, 2 = 1st pixel of 2nd walk, etc. 0 123 -1 1 2 3 4 123 5 4 0 f igure 10. p ass 2 o f t wo -p ass devices incorporated video imaging products 2-13 LF2301 image resampling sequencer 08/16/2000Clds.2301-h storage temperature ........................................................................................................... C65c to +150c operating ambient temperature ........................................................................................... C55c to +125c v cc supply voltage with respect to ground ............................................................................ C0.5 v to +7. 0v input signal with respect to ground ............................................................................... C0.5 v to v cc + 0.5 v signal applied to high impedance output ...................................................................... C0.5 v to v cc + 0.5 v output current into low outputs ................................................................................................ ............. 25 ma latchup current ................................................................................................................ ............... > 400 ma m aximum r atings above which useful life may be impaired (notes 1, 2, 3, 8) o perating c onditions to meet specified electrical and switching characteristics mode temperature range (ambient) supply voltage active operation, commercial 0c to +70c 4.75 v v cc 5.25 v active operation, military C55c to +125c 4.50 v v cc 5.50 v symbol parameter test condition min typ max unit v oh output high voltage v cc = min., i oh = C2.0 ma 2.4 v v ol output low voltage v cc = min., i ol = 4.0 ma 0.4 v v ih input high voltage 2.0 v cc v v il input low voltage (note 3) 0.0 0.8 v i ix input current ground v in v cc (note 12) 10 a i oz output leakage current ground v out v cc (note 12) 10 a i cc1 v cc current, dynamic (notes 5, 6) 75 ma i cc2 v cc current, quiescent (note 7) 5ma c in input capacitance t a = 25c, f = 1 mhz 10 pf c out output capacitance t a = 25c, f = 1 mhz 10 pf e lectrical c haracteristics over operating conditions (note 4) devices incorporated LF2301 image resampling sequencer 2-14 08/16/2000Clds.2301-h video imaging products 1234567890123456789012345678901212345678901234 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 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123456789012345678901234567890121234567890123 4 123456789012345678901234567890121234567890123 4 1234567890123456789012345678901212345678901234 1234567890123456 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 123456789012345 6 1234567890123456 LF2301C 66 * 55 25 symbol parameter min max min max min max t cyc cycle time 66 55 25 t pw clock pulse width 30 25 10 t s input setup time 20 18 10 t h input hold time 2 2 0 t hi input hold time, inter 10 10 5 t d output delay 35 27 18 t de output delay, end 45 37 18 t ena three-state output enable delay (note 11) 35 27 15 t dis three-state output disable delay (note 11) 20 18 15 c ommercial o perating r ange (0c to +70c) notes 9, 10 (ns) switching characteristics m ilitary o perating r ange (-55c to +125c) notes 9, 10 (ns) 123456789012345678901234 1 2345678901234567890123 4 1 2345678901234567890123 4 123456789012345678901234 *d iscontinued s peed g rade LF2301C 66 * 55 * 30 * symbol parameter min max min max min max t cyc cycle time 66 55 30 t pw clock pulse width 30 25 10 t s input setup time 20 18 12 t h input hold time 2 2 0 t hi input hold time, inter 10 10 6 t d output delay 35 27 20 t de output delay, end 45 37 20 t ena three-state output enable delay (note 11) 35 27 18 t dis three-state output disable delay (note 11) 20 18 18 devices incorporated video imaging products 2-15 LF2301 image resampling sequencer 08/16/2000Clds.2301-h s witching w aveforms : d ata o utputs and c ontrol l ines clk t cyc t pw t pw t s t hi high impedance high impedance end uwri czero, acc, done x11-0, ca7-0 noop oeta inter t ena t dis t s t h t h t s t de t ena high impedance u11-0 t dis t d t ena t dis s witching w aveforms : d ata i nputs (p arameter s torage ) clk t cyc t pw t pw t s t h p 11-0 ldr wen b 3-0 devices incorporated LF2301 image resampling sequencer 2-16 08/16/2000Clds.2301-h video imaging products 1. maximum ratings indicate stress specifications only. functional oper- ation of these products at values beyond those indicated in the operating condi- tions table is not implied. exposure to maximum rating conditions for ex- tended periods may affect reliability. 2. the products described by this spec- ification include internal circuitry de- signed to protect the chip from damag- ing substrate injection currents and ac- cumulations of static charge. neverthe- less, conventional precautions should be observed during storage, handling, and use of these circuits in order to avoid exposure to excessive electrical stress values. 3. this device provides hard clamping of transient undershoot and overshoot. in- put levels below ground or above v cc will be clamped beginning at C0.6 v and v cc + 0.6 v. the device can withstand indefinite operation with inputs in the range of C0.5 v to +7.0 v. device opera- tion will not be adversely affected, how- ever, input current levels will be well in excess of 100 ma. 4. actual test conditions may vary from those designated but operation is guar- anteed as specified. 5. supply current for a given applica- tion can be accurately approximated by: where n = total number of device outputs c = capacitive load per output v = supply voltage f = clock frequency 6. tested with no output load at 15 mhz clock rate. 7. tested with all inputs within 0.1 v of v cc or ground, no load. 8. these parameters are guaranteed but not 100% tested. ncv f 4 2 notes 9. ac specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 v (except t dis test), and input levels of nominally 0 to 3.0 v. output loading may be a resistive divider which provides for specified i oh and i ol at an output voltage of v oh min and v ol max respectively. alternatively, a diode bridge with upper and lower current sources of i oh and i ol respectively, and a balancing voltage of 1.5 v may be used. parasitic capacitance is 30 pf minimum, and may be distributed. this device has high-speed outputs ca- pable of large instantaneous current pulses and fast turn-on/turn-off times. as a result, care must be exercised in the testing of this device. the following measures are recommended: a. a 0.1 f ceramic capacitor should be installed between v cc and ground leads as close to the device under test (dut) as possible. similar capacitors should be installed between device v cc and the tester common, and device ground and tester common. b. ground and v cc supply planes must be brought directly to the dut socket or contactor fingers. c. input voltages should be adjusted to compensate for inductive ground and v cc noise to maintain required dut in- put levels relative to the dut ground pin. 10. each parameter is shown as a mini- mum or maximum value. input require- ments are specified from the point of view of the external system driving the chip. setup time, for example, is specified as a minimum since the external system must supply at least that much time to meet the worst-case requirements of all parts. responses from the internal cir- cuitry are specified from the point of view of the device. output delay, for example, is specified as a maximum since worst- case operation of any device always pro- vides data within that time. 11. for the t ena test, the transition is measured to the 1.5 v crossing point with datasheet loads. for the t dis test, the transition is measured to the 200mv level from the measured steady-state output voltage with 10ma loads. the balancing volt- age, v th , is set at 3.5 v for z-to-0 and 0-to-z tests, and set at 0 v for z- to-1 and 1-to-z tests. 12. these parameters are only tested at the high temperature extreme, which is the worst case for leakage current. s1 i oh i ol v th c l dut oe 0.2 v t dis t ena 0.2 v 1.5 v 1.5 v 3.5v vth 1 z 0 z z 1 z 0 1.5 v 1.5 v 0v vth v ol * v oh * v ol * v oh * measured v ol with i oh = C10ma and i ol = 10ma measured v oh with i oh = C10ma and i ol = 10ma f igure b. t hreshold l evels f igure a. o utput l oading c ircuit devices incorporated video imaging products 2-17 LF2301 image resampling sequencer 08/16/2000Clds.2301-h 1 2 3 4 5 6 7 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 68 67 66 65 64 63 36 35 37 38 39 41 30 29 31 32 33 34 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 40 top view 8 96261 28 27 42 43 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 gnd x 9 x 10 x 11 p 11 p 10 p 9 p 8 p 7 gnd u 9 u 8 u 7 u 6 u 5 u 4 u 3 gnd u 2 u 1 u 0 done end inter oeta init p 6 p 5 p 4 p 3 p 2 p 1 p 0 clk gnd v cc noop ldr b 0 b 1 b 2 b 3 wen gnd x o ca 7 ca 6 ca 5 ca 4 ca 3 ca 2 gnd v cc ca 1 ca 0 czero acc uwri u 11 u 10 ordering information 0c to +70c c ommercial s creening speed 55 ns 25 ns plastic j-lead chip carrier (j2) LF2301jc55 LF2301jc25 68-pin devices incorporated LF2301 image resampling sequencer 2-18 08/16/2000Clds.2301-h video imaging products 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 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23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1 23456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 1 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 ordering information speed C55c to +125c mil-std-883 c ompliant C55c to +125c c ommercial s creening ceramic pin grid array (g1) 68-pin a b c d e f g h j k l top view through package (i.e., component side pinout) 12345 6 7 8 9 10 11 wen init inter done u 1 gnd u 4 u 6 u 8 u 10 u 11 b 3 b 2 uwri acc b 1 b 0 czero ca 0 ldr noop ca 1 v cc v cc gnd gnd ca 2 clk p 0 ca 3 ca 4 p 1 p 2 ca 5 ca 6 p 3 p 4 ca 7 x 0 p 5 p 6 p 9 p 11 x 10 gnd x 7 x 5 x 3 x 1 gnd oeta end u 0 u 2 u 3 u 5 u 7 u 9 gnd p 7 p 8 p 10 x 11 x 9 x 8 x 6 x 4 x 2 0c to +70c c ommercial s creening discontinued package |
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